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? semiconductor components industries, llc, 2010 september, 2010 ? rev. 5 1 publication order number: ncp1529/d ncp1529 1.7mhz, 1a, high efficiency, low ripple, adjustable output voltage step-down converter the ncp1529 step ? down dc ? dc converter is a monolithic integrated circuit for portable applications powered from one cell li ? ion or three cell alkaline/nicd/n imh batteries. the device is able to deliver up to 1.0 a on an output voltage range externally adjustable from 0.9 v to 3.9 v or fixed at 1.2 v or 1.35 v. it uses synchronous rectification to increase efficiency and reduce external part count. the device also has a built ? in 1.7 mhz (nominal) oscillator which reduces component size by allowing a small inductor and capacitors. automatic switching pwm/pfm mode offers improved system efficiency. additional features include integrated soft ? start, cycle ? by ? cycle current limiting and thermal shutdown protection. the ncp1529 is available in a space saving, low profile 2x2x0.5 mm udfn6 package and tsop ? 5 package. features ? up to 96% efficiency ? best in class ripple, including pfm mode ? source up 1.0 a ? 1.7 mhz switching frequency ? adjustable from 0.9 v to 3.9 v or fixed at 1.2 v or 1.35 v ? synchronous rectification for higher efficiency ? 2.7 v to 5.5 v input voltage range ? low quiescent current 28 a ? shutdown current consumption of 0.3 a ? thermal limit protection ? short circuit protection ? all pins are fully esd protected ? these are pb ? free devices typical applications ? cellular phones, smart phones and pdas ? digital still cameras ? mp3 players and portable audio systems ? wireless and dsl modems ? usb powered devices ? portable equipment gnd vin en sw fb off on v in c in c out r1 r2 c ff figure 1. typical application for adjustable version l v out gnd vin en sw fb off on v in c in c out figure 2. typical application for fixed version l v out tsop ? 5 sn suffix case 483 http://onsemi.com marking diagram 1 5 dxj = specific device code a = assembly location y = year w = work week = pb ? free package (note: microdot may be in either location) 1 5 dxjayw xxm 1 2 3 6 5 4 udfn6 mu suffix case 517ab xx = specific device code m = date code = pb ? free package (note: microdot may be in either location) see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information
ncp1529 http://onsemi.com 2 pin function description pin tsop ? 5 pin udfn6 pin name type description 1 6 en analog input enable for switching regulators. this pin is active high and is turned off by logic low on this pin. 2 2,4,7 (note 1) gnd analog / power ground this pin is the gnd reference for the nfet power stage and the analog section of the ic. the pin must be connected to the system ground. 3 5 sw analog output connection from power mosfets to the inductor. 4 3 vin analog / power input power supply input for the pfet power stage, analog and digital blocks. the pin must be decoupled to ground by a 4.7 f ceramic capacitor. 5 1 fb analog input feedback voltage from the output of the power supply. this is the input to the error amplifier. 1. exposed pad for udfn6 package, named pin 7, must be connected to system ground. figure 3. pin connections ? tsop ? 5 figure 4. pin connections ? udfn6 (top view) 1 2 3 5 4 en gnd sw fb vin 1 2 3 6 4 fb gnd vin en gnd pin connections 5 sw 7 (top view) performances figure 5. efficiency vs output current v in = 3.6 v, v out = 3.3 v 100 90 80 70 60 50 40 30 20 10 0 0 500 1000 i out (ma) efficiency (%)
ncp1529 http://onsemi.com 3 functional block diagram gnd vin v battery 4.7 f en enable logic control & thermal shutdown pwm/pfm control i limit reference voltage fb sw q1 10 f 18 pf r1 r2 2.2 h q2 figure 6. simplified block diagram
ncp1529 http://onsemi.com 4 maximum ratings rating symbol value unit minimum voltage all pins v min ? 0.3 v maximum voltage all pins (note 2) v max 7.0 v maximum voltage en v max v in + 0.3 v thermal resistance, junction ? to ? air (tsop ? 5 package) thermal resistance using tsop ? 5 recommended board layout (note 9) r ja 300 110 c/w thermal resistance, junction ? to ? air (udfn6 package) thermal resistance using udfn6 recommended board layout (note 9) r ja 220 40 c/w operating ambient temperature range (notes 7 and 8) t a ? 40 to 85 c storage temperature range t stg ? 55 to 150 c junction operating temperature (notes 7 and 8) t j ? 40 to 150 c latchup current maximum rating (t a = 85 c) (note 5) other pins lu 100 ma esd withstand voltage (note 4) human body model machine model v esd 2.0 200 kv v moisture sensitivity level (note 6) msl 1 per ipc stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = 25 c. 3. according to jedec standard jesd22 ? a108b. 4. this device series contains esd protection and exceeds the following tests: human body model (hbm) per jedec standard: jesd22 ? a114. machine model (mm) per jedec standard: jesd22 ? a115. 5. latchup current maximum rating per jedec standard: jesd78. 6. jedec standard: j ? std ? 020a. 7. in applications with high power dissipation (low v in , high i out ), special care must be paid to thermal dissipation issues. board design considerations ? thermal dissipation vias, traces or planes and pcb material ? can significantly improve junction to air thermal resistance r ja (for more information, see design and layout consideration section). environmental conditions such as ambient temperature t a brings thermal limitation on maximum power dissipation allowed. the following formula gives calculation of maximum ambient temperature allowed by the application: t a max = t j max ? (r ja x p d ) where: t j is the junction temperature, p d is the maximum power dissipated by the device (worst case of the application), and r ja is the junction ? to ? ambient thermal resistance. 8. to prevent permanent thermal damages, this device include a thermal shutdown which engages at 180 c (typ). 9. board recommended tsop ? 5 and udfn6 layouts are described on layout considerations section. figure 7. maximum output current, t a = 45 c 0 200 400 600 800 1000 1200 ? 40 ? 200 20 406080 t a , ambient temperature ( c) p d , power dissipation (mw) figure 8. power derating tsop ? 5 udfn6 0 200 400 600 800 1000 1200 2.7 3.2 3.7 4.2 4.7 5.2 v in , input voltage (v) i outmax , maximum output cur- rent (ma) tsop ? 5 udfn6
ncp1529 http://onsemi.com 5 electrical characteristics (typical values are referenced to t a = +25 c, min and max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted, operating conditions v in = 3.6 v, v out = 1.2 v, unless otherwise noted.) rating conditions symbol min typ max unit input voltage input voltage range v in 2.7 ? 5.5 v quiescent current no switching, no load i q ? 28 39 a standby current en low i stb ? 0.3 1.0 a under voltage lockout v in falling v uvlo 2.2 2.4 2.55 v under voltage hysteretis v uvloh ? 100 ? mv analog and digital pin positive going input high voltage threshold v ih 1.2 ? ? v negative going input high voltage threshold v il ? ? 0.4 v en threshold hysteresis v enh ? 100 ? mv en high input current en = 3.6 v i enh ? 1.5 ? a output feedback voltage level adjustable version fixed version at 1.2 v fixed version at 1.35 v v fb ? ? ? 0.6 1.2 1.35 ? ? ? v output voltage range (notes 10, 11) usb or 5 v rail powered applications (v in from 4.3 v to 5.5 v) (note 12) v out 0.9 0.9 ? ? 3.3 3.9 v output voltage accuracy room temperature (note 13) overtemperature range v out ? ? 3 1 2 ? +3 % maximum output current (note 10) i outmax 1 ? ? a output voltage load regulation overtemperature load = 100 ma to 1000 ma (pwm mode) load = 0 ma to 100 ma (pfm mode) v loadr ? ? ? 0.9 1.1 ? ? % load transient response rise/fall time 1 s 10 ma to 100 ma load step (pfm to pwm mode) 200 ma to 600 ma load step (pwm to pwm mode) v loadt ? ? 40 85 ? ? mv output voltage line regulation load = 100 ma v in = 2.7 v to 5.5 v v liner ? 0.05 ? % line transient response load = 100 ma 3.6 v to 3.2 v line step (fall time = 50 s) v linet ? 6.0 ? mv pp output voltage ripple i out = 0 ma i out = 300 ma v ripple ? ? 8.0 3.0 ? ? mv pp switching frequency f sw 1.2 1.7 2.2 mhz duty cycle d ? ? 100 % soft ? start time time from en to 90% of output voltage t start ? 310 500 s power switches high ? side mosfet on ? resistance r onhs ? 400 ? m low ? side mosfet on ? resistance r onls ? 300 ? m high ? side mosfet leakage current i leakhs ? 0.05 ? a low ? side mosfet leakage current i leakls ? 0.01 ? a protection dc ? dc short circuit protection peak inductor current i pk ? 1.6 ? a thermal shutdown threshold t sd ? 180 ? c thermal shutdown hysteresis t sdh ? 40 ? c 10. functionality guaranteed per design and characterization. 11. whole output voltage range is available for adjustable versions only. by topology, the maximum output voltage will be equal or lower than the input voltage. 12. see chapter ?usb or 5 v rail powered applications?. 13. for adjustable versions only, the overall output voltage tolerance depends upon the accuracy of the external resistor (r1 an d r2). specified value assumes that external resistor have 0.1% tolerance.
ncp1529 http://onsemi.com 6 table of graphs typical characteristics for step ? down converter figure efficiency vs. output current 10, 11, 12 i q on quiescent current, pfm no load vs. input voltage 9 i q off standby current, en low vs. input voltage 8 f sw switching frequency vs. ambient temperature 13 v loadr load regulation vs. load current 14 v loadt load transient response 16, 17 v liner line regulation vs. output current 15 v linet line transient response 18, 19 t start soft start 20 i pk short circuit protection 21 v uvlo under voltage lockout threshold vs. ambient temperature 22 v il , v ih enable threshold vs. ambient temperature 23 p, g phase & gain performance 24
ncp1529 http://onsemi.com 7 i stb , standby current ( a) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in , input voltage (v) figure 9. standby current vs. input voltage (enable = 0, temperature = 25 c) 27 28 29 30 31 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v in , input voltage (v) figure 10. quiescent current vs. input voltage (open loop, feedback = 1, temperature = 25 c) i q , quiescent current ( a) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 efficiency (%) i out , output current (ma) figure 11. efficiency vs. output current (v in = 3.3 v, v out = 1.2 v) 25 c 85 c ? 40 c 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 efficiency (%) i out , output current (ma) figure 12. efficiency vs. output current (v out = 1.2 v, temperature = 25 c) 5.5 v v bat = 2.7 v 3.3 v efficiency (%) i out , output current (ma) figure 13. efficiency vs. output current (v in = 3.6 v, temperature = 25 c) v out = 0.9 v 3.3 v 1.2 v 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 ? 60 ? 20 20 60 100 t a , ambient temperature ( c) figure 14. switching frequency vs. ambient temperature (v out = 1.2 v, i out = 200 ma) switching frequency (mhz) v in = 2.7 v 3.6 v 5.5 v
ncp1529 http://onsemi.com 8 ? 3.0 ? 2.0 ? 1.0 0.0 1.0 2.0 3.0 0 200 400 600 800 1000 load regulation (%) i out , output current (ma) figure 15. load regulation vs. output current (v in = 5.5 v, v out = 1.2 v) 25 c 85 c ? 40 c ? 3.0 ? 2.0 ? 1.0 0 1.0 2.0 3.0 2.7 3.2 3.7 4.2 4.7 5.2 i out = 800 ma 100 ma 1 ma v in , input voltage (v) figure 16. line regulation vs. input voltage (v out = 1.2 v, temperature = 25 c) line regulation (%) figure 17. 10 ma to 100 ma load transient in 1 s (v in = 3.6 v, v out = 1.2 v, temperature = 25 c) figure 18. 200 ma to 600 ma load transient in 1 s (v in = 3.6 v, v out = 1.2 v, temperature = 25 c) figure 19. 3.0 v to 3.6 v line transient, rise = 50 s (v in = 1.2 v, i out = 100 ma, temperature = 25 c) figure 20. 3.6 v to 3.0 v line transient, fall = 50 s (v in = 1.2 v, i out = 100 ma, temperature = 25 c)
ncp1529 http://onsemi.com 9 figure 21. typical soft ? start (v in = 3.6 v, v out = 1.2 v, i out = 100 ma, temperature = 25 c) figure 22. short ? circuit protection (v in = 3.6 v, v out = 1.2 v, i out = cc, temperature = 25 c) 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 ? 50 ? 25 0 25 50 75 100 125 t a , ambient temperature ( c) figure 23. undervoltage lockout threshold vs. ambient temperature undervoltage lockout threshold (v) uvlofall uvlorise 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 ? 40 ? 15 10 35 60 85 v il v ih t a , ambient temperature ( c) figure 24. enable threshold voltages vs. ambient temperature enable threshold voltages (v) ? 50 ? 30 ? 10 10 30 50 70 10 100 1000 10000 100000 1000000 ? 160 ? 120 ? 80 ? 40 0 40 80 120 160 200 phase gain frequency (hz) figure 25. phase and gain performance (v in = 3.6 v, v out = 1.2 v, i out = 200 ma, temperature = 25 c) gain (db) phase ( )
ncp1529 http://onsemi.com 10 dc/dc operation description detailed description the ncp1529 uses a constant frequency, current mode step ? down architecture. both the main (p ? channel mosfet) and synchronous (n ? channel mosfet) switches are internal. the output voltage is set by an external resistor divider in the range of 0.9 v to 3.9 v and can source at least 1a. the ncp1529 works with two modes of operation; pwm/pfm depending on the current required. in pwm mode, the device can supply voltage with a tolerance of 3% and 90% efficiency or better. lighter load currents cause the device to automatically switch into pfm mode to reduce current consumption and extended battery life. additional features include soft ? start, undervoltage protection, current overload protection and thermal shutdown protection. as shown on figure 1, only six external components are required. the part uses an internal reference voltage of 0.6 v. it is recommended to keep ncp1529 in shutdown mode until the input voltage is 2.7 v or higher. pwm operating mode in this mode, the output voltage of the device is regulated by modulating the on ? time pulse width of the main switch q1 at a fixed 1.7 mhz frequency. the switching of the pmos q1 is controlled by a flip ? flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the sum of the sensed current signal and compensation ramp. the driver switches on and off the upper side transistor (q1) while the lower side transistor is switched off then on. at the beginning of each cycle, the main switch q1 is turned on by the rising edge of the internal oscillator clock. the inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error amplifier?s voltage. once this has occurred, the pwm comparator resets the flip ? flop, q1 is turned off while the synchronous switch q2 is turned on. q2 replaces the external schottky diode to reduce the conduction loss and improve the efficiency. to avoid overall power loss, a certain amount of dead time is introduced to ensure q1 is completely turned off before q2 is being turned on. v out i sw figure 26. pwm switching waveforms (v in = 3.6 v, v out = 1.2 v, i out = 600 ma, temperature = 25 c) v sw pfm operating mode under light load conditions, the ncp1529 enters in low current pfm mode of operation to reduce power consumption. the output regulation is implemented by pulse frequency modulation. if the output voltage drops below the threshold of pfm comparator a new cycle will be initiated by the pfm comparator to turn on the switch q1. q1 remains on during the minimum on time of the structure while q2 is in its current source mode. the peak inductor current depends upon the drop between input and output voltage. after a short dead time delay where q1 is switched off, q2 is turned in its on state. the negative current detector will detect when the inductor current drops below zero and sends a signal to turn q2 to current source mode to prevent a too large deregulation of the output voltage. when the output voltage falls below the threshold of the pfm comparator, a new cycle starts immediately. v out i sw figure 27. pfm switching waveforms (v in = 3.6 v, v out = 1.2 v, i out = 0 ma, temperature = 25 c) v sw
ncp1529 http://onsemi.com 11 soft ? start the ncp1529 uses soft ? start to limit the inrush current when the device is initially powered up or enabled. soft start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. during startup, a pulsed current source charges the internal soft ? start capacitor to provide gradually increasing reference voltage. when the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. cycle ? by ? cycle current limitation from the block diagram, an i lim comparator is used to realize cycle ? by ? cycle current limit protection. the comparator compares the sw pin voltage with the reference voltage, wh ich is biased by a constant current. if the inductor current reaches the limit, the i lim comparator detects the sw voltage falling below the reference voltage and releases the signal to turn off the switch q1. the cycle ? by ? cycle current limit is set at 1600 ma (nom). low dropout operation the ncp1529 offers a low input to output voltage difference. the ncp1529 can operate at 100% duty cycle. in this mode the pmos (q1) remains completely on. the minimum input voltage to maintain regulation can be calculated as: v out v out(max) i out r ds(on) _r inductor (eq. 1) ? v out : output voltage (v) ? i out : max output current ? r ds(on) : p ? channel switch r ds(on) ? r inductor : inductor resistance (dcr) undervoltage lockout the input voltage v in must reach 2.4 v (typ) before the ncp1529 enables the dc/dc converter output to begin the start up sequence (see soft ? start section). the uvlo threshold hysteresis is typically 100 mv. shutdown mode forcing this pin to a voltage below 0.4 v will shut down the ic. in shutdown mode, the internal reference, oscillator and most of the control circuitries are turned off. therefore, the typical current consumption will be 0.3 a (typical value). applying a voltage above 1.2 v to en pin will enable the dc/dc converter for normal operation. the device will go through soft ? start to normal operation. thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. if the junction temperature exceeds 180 c, the device shuts down. in this mode all power transistors and control circuits are turned off. the device restarts in soft ? start after the temperature drops below 140 c. this feature is provided to prevent catastrophic failures from accidental device overheating. short circuit protection when the output is shorted to ground, the device limits the inductor current. the duty ? cycle is minimum and the consumption on the input line is 550 ma (typ). when the short circuit condition is removed, the device returns to the normal mode of operation. usb or 5 v rail powered applications for usb or 5 v rail powered applications, ncp1529 is able to supply voltages up to 3.9 v, 600 ma, operating in pwm mode only, with high efficiency (figure 28), low output voltage ripple and good load regulation results over all current range (figure 29). 40 45 50 55 60 65 70 75 80 85 90 95 100 0 200 400 600 800 1000 efficiency (%) i out , output current (ma) figure 28. efficiency vs. output current (v in = 5.0 v, v out = 3.9 v) 25 c 85 c ? 40 c ? 3.0 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 200 400 600 800 1000 load regulation (%) i out , output current (ma) figure 29. load regulation vs. output current (v in = 5.0 v, v out = 3.9 v) 25 c 85 c ? 40 c
ncp1529 http://onsemi.com 12 application information output voltage selection in case of adjustable versions, the output voltage is programmed through an external resistor divider connected from v out to fb then to gnd. for low power consumption and noise immunity, the resistor from fb to gnd (r2) should be in the [100k ? 600k] range. if r2 is 200 k given the v fb is 0.6 v, the current through the divider will be 3.0 a. the formula below gives the value of v out , given the desired r1 and the r1 value: v out v fb (1 r1 r2) (eq. 2) ? v out : output voltage (v) ? v fb : feedback voltage = 0.6 v ? r1: feedback resistor from v out to fb ? r2: feedback resistor from fb to gnd input capacitor selection in pwm operating mode, the input current is pulsating with large switching noise. using an input bypass capacitor can reduce the peak current transients drawn from the input supply source, thereby reducing switching noise significantly. the capacitance needed for the input bypass capacitor depends on the source impedance of the input supply. the maximum rms current occurs at 50% duty cycle with maximum output current, which is io, max/2. for ncp1529, a low profile ceramic capacitor of 4.7 f should be used for most of the cases. for effective bypass results, the input capacitor should be placed as close as possible to the vin pin table 1. list of input capacitors manufacturer part number case size value ( f) dc bias (v) technology murata grm15 series 0402 4.7 6.3 x5r murata grm18 series 0603 4.7 10 x5r tdk c1608 series 0603 4.7 6.3 x5r tdk c1608 series 0603 4.7 10 x5r output l ? c filter design considerations th e ncp1529 operates at 1.7 mhz frequency and uses current mode architecture. the correct selection of the output filter ensures good stability and fast transient response. due to the nature of the buck converter, the output l ? c filter must be selected to work with internal compensation. for ncp1529, the internal compensation is internally fixed and it is optimized for an output filter of l = 2.2 h and c out = 10 f. the corner frequency is given by: f 1 2 l c out 1 2 2.2 h 10 f 34 khz (eq. 3) the device operates with inductance value of 2.2 h. if the corner frequency is moved, it is recommended to check the loop stability depending of the accepted output ripple voltage and the required output current. take care to check the loop stability. the phase margin is usually higher than 45 . table 2. l ? c filter example inductance (l) output capacitor (c out ) 2.2 h 10 f 4.7 h 4.7 f inductor selection the inductor parameters directly related to device performances are saturation current and dc resistance and inductance value. the inductor ripple current ( i l ) decreases with higher inductance: i l v out l f sw 1
v out v in (eq. 4) ? i l : peak to peak inductor ripple current ? l: inductor value ? f sw : switching frequency the saturation current of the inductor should be rated higher than the maximum load current plus half the ripple current: i l(max) i o(max) i l 2 (eq. 5) ? i l(max) : maximum inductor current ? i o(max) : maximum output current the inductor?s resistance will factor into the overall efficiency of the converter. for best performances, the dc resistance should be less than 0.3 for good efficiency.
ncp1529 http://onsemi.com 13 table 3. list of inductors manufacturer part number case size (mm) height max (mm) l ( h) dcr typ ( ) dcr max ( ) rated current (ma) inductance drop rated current (ma) temperature drop structure coilcraft do1605t-222 5.5 x 4.2 1.8 2.2 na 0.070 1800 (-10%) 1700 (+40 c) wire wound coilcraft epl3015-222 3.0 x 3.0 1.5 2.2 0.082 0.094 1600 (-30%) 2000 (+40 c) wire wound coilcraft epl2014-222 2.0 x 2.0 1.4 2.2 0.120 0.132 1300 (-30%) 1810 (+40 c) wire wound murata lqm2hpn2r2 2.5 x 2.0 1.0 2.2 0.080 0.100 na 1300 (+40 c) multilayer murata lqh3npn2r2 3.0 x 3.0 1.2 2.2 0.065 0.085 1150 (-30%) 1460 (+40 c) wire wound murata lqh44pn2r2 4.0 x 4.0 1.8 2.2 0.049 0.059 2500 (-30%) 1800 (+40 c) wire wound tdk mlp2520s2r2l 2.5 x 2.0 1.0 2.2 0.080 0.104 1300 (-30%) na multilayer tdk vls252010t2r2 2.0 x 1.6 1.2 2.2 0.158 0.190 1400 (-30%) 1100 (+40 c) wire wound wurth elec 744 029 002 2.8 x 2.8 1.35 2.2 0.088 0.105 1150 (-35%) 1700 (+40 c) wire wound output capacitor selection selecting the proper output capacitor is based on the desired output ripple voltage. ceramic capacitors with low esr values will have the lowest output ripple voltage and are strongly recommended. the output capacitor requires either an x7r or x5r dielectric. the output ripple voltage in pwm mode is given by: v out i l 1 4 f sw c out esr (eq. 6) table 4. list of output capacitors manufacturer part number case size value ( f) dc bias (v) technology murata grm15 series 0402 4.7 6.3 x5r murata grm18 series 0603 4.7 10 x5r murata grm18 series 0603 10 6.3 x5r tdk c1608 series 0603 4.7 6.3 x5r tdk c1608 series 0603 4.7 10 x5r tdk c1608 series 0603 10 6.3 x5r feed ? forward capacitor selection (adjustable only) the feed-forward capacitor sets the feedback loop response and acts on soft-start time. a minimum 18 pf feed-forward capacitor is needed to ensure loop stability. having feed-forward capacitor of 1 nf or higher can increase soft ? start time and reduce inrush current. choose a small ceramic capacitor x7r or x5r or cog dielectric.
ncp1529 http://onsemi.com 14 layout considerations electrical layout considerations implementing a high frequency dc ? dc converter requires respect of some rules to get a powerful portable application. good layout is key to prevent switching regulators to generate noise to application and to themselves. electrical layout guide lines are: ? use short and large traces when large amount of current is flowing. ? keep the same ground reference for input and output capacitors to minimize the loop formed by high current path from the battery to the ground plane. ? isolate feedback pin from the switching pin and the current loop to protect against any external parasitic signal coupling. add a feed ? forward capacitor between v out and fb which adds a zero to the loop and participates to the good loop stability. a 18 pf capacitor is recommended to meet compensation requirements. a four layer pcb with a ground plane and a power plane will help ncp1529 noise immunity and loop stability. thermal layout considerations high power dissipation in small package leads to thermal consideration such as: ? enlarge v in trace and added several vias connected to power plane. ? connect gnd pin to top plane. ? join top, bottom and each ground plane together using several free vias in order to increase radiator size. for high ambient temperature and high power dissipation requirements, udfn6 package using exposed pad connected to main radiator is recommended. refer to notes 7, 8, and 9. figure 30. tsop ? 5 recommended board layout figure 31. udfn6 recommended board layout v out trace fb trace sw trace v in trace gnd plane en trace sw trace v out trace fb trace v in trace gnd plane en trace ordering information device nominal output voltage marking package shipping ? NCP1529ASNT1G adj dxj tsop ? 5 3000 / tape & reel ncp1529mutbg adj tl udfn6 3000 / tape & reel ncp1529mu12tbg 1.2 v tc ncp1529mu135tbg 1.35 v rc ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1529 http://onsemi.com 15 package dimensions tsop ? 5 case 483 ? 02 issue g notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 l 1.25 1.55 m 0 10 s 2.50 3.00 123 54 s a g l b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 t seating plane 0.05 k m detail z detail z
ncp1529 http://onsemi.com 16 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. c a seating plane d b e 0.10 c a3 a a1 2x 2x 0.10 c udfn6 2x2, 0.65p case 517ab ? 01 issue a dim a min max millimeters 0.45 0.55 a1 0.00 0.05 a3 0.127 ref b 0.25 0.35 d 2.00 bsc d2 1.50 1.70 0.80 1.00 e 2.00 bsc e2 e 0.65 bsc k 0.25 0.35 l pin one reference 0.08 c 0.10 c 6x a 0.10 c note 3 l e e2 b b 3 6 6x 1 k 4 6x 6x 0.05 c 4x d2 bottom view 0.20 --- *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.47 0.40 0.65 1.70 2.30 1 dimensions: millimeters 6x 0.95 pitch 6x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1529/d the product described herein (ncp1529), may be covered by the following u.s. patents: tbd. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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